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Radiation Effects and Mitigation Techniques for FPGAs Fernanda Lima Kastensmidt Universidade Federal do Rio Grande do Sul (UFRGS) Contact: [email protected] Field Programmable Gate Arrays A type of gate array that is programmed in the field rather than in a semiconductor fab. It contains programmable logic components called "logic blocks", and a hierarchy of configurable interconnects that allow the blocks to be "wired together“. Logic blocks: can be configured to perform complex combinational functions (combinational logic) include memory elements (sequential logic) It may contain embedded memories and microprocessors SERESSA 2011 – Fernanda Kastensmidt FPGA Design Flow Design Synthesis optimizations Logic mapping Placement Routing configuration bitstream … 101001110100000111… User’s design mapped into the FPGA SERESSA 2011 – Fernanda Kastensmidt FPGA Summary Programmable Element ANTIFUSE • electrically programmable switch forms a low resistance path between two metal layers. Characteristics Example of Fabricants FLASH • electrically programmable transistors hold the configuration that controls a pass transistors or multiplexers connected to predefined metal layers SRAM • the state of a static latch controls pass transistors or multiplexers connected to predefined metal layers • Configuration is NO volatile • Configuration is NO volatile • Configuration is volatile • One-time configurable • Re-configurable • Re-configurable SERESSA 2011 – Fernanda Kastensmidt Effects of ionizing radiation Single Event Effects (SEE) Soft Errors Hard Errors Single Event Transient (SET) Functional Interrupt (SEFI) Single Event Upset (SEU) Single Event Latchup (SEL) Gate Rupture (SEGR) Single Event Burnout (SEB) Total Ionizing Dose (TID) Displacement Damage (DD) 6 Kastensmidt SERESSA 2011 – Fernanda Radiation effects in FPGA Single Event Effects (SEE) Soft Errors Hard Errors Single Event Transient (SET) Functional Interrupt (SEFI) Single Event Upset (SEU) Single Event Latchup (SEL) Gate Rupture (SEGR) Single Event Burnout (SEB) Total Ionizing Dose (TID) Displacement Damage (DD) 7 Kastensmidt SERESSA 2011 – Fernanda SEU in Memory Elements SRAM cell OFF OFF 01 OFF WL OFF WL 01 gnd BIT-FLIP P N N P ionization 8 Kastensmidt SERESSA 2011 – Fernanda SET in Logic Gates Inverter cell 1 OFF 0 gnd P N N P ionization 9 Kastensmidt SERESSA 2011 – Fernanda SET in Combinational Circuits Not all SETs are captured by a memory cell. They can be: Logical masked Electrical masked Latch window masked Logical masked e0 e1 e2 a3 1 0 0 0 1 1 1 10 Kastensmidt SERESSA 2011 – Fernanda Q SET in Combinational Circuits Not all SETs are captured by a memory cell. They can be: Logical masked Electrical masked Latch window masked Electrical masked e0 e1 e2 a3 1 1 1 0 1 Negligible pulse 0 0 0 SERESSA 2011 – Fernanda Kastensmidt Q SET in Combinational Circuits Not all SETs are captured by a memory cell. They can be: Logical masked Electrical masked Latch window masked Latch window masked e0 e1 e2 a3 1 1 1 0 1 0 0 0 clk edge 12 Kastensmidt SERESSA 2011 – Fernanda Q TID Effects in CMOS circuits Effects: • shifts in the NMOS transistor Voltage Threshold (Vth) • increase of leakage current in transistors • Flash transistors: lost of gate charge Because oxide dimensions reduce with the advance of technology, TID effects have been reduced. SERESSA 2011 – Fernanda Kastensmidt Using FPGA under Radiation Analyze SEU and SET effects in FPGA architecture and your configured design Use hardening techniques if needed Qualify FPGA and your design under radiation User implementation: Hardening techniques at hardware description language (your configured design): VHDL or Verilog design Vendor implementation: Hardening techniques at the FPGA matrix logic gates and flip-flops FPGA SERESSA 2011 – Fernanda Kastensmidt Synthesis Tool Synthesis attributes must be set on your design tool. For example by using Synplify, Mentor or Synopsys. According to the tool and vendor there are: tmr attributes can be turned on or off and it can be local or global. Examples: Module br_core (.............) /* synthesis syn_radhardlevel="tmr" */; reg hdw_loss_arb /* synthesis syn_radhardlevel="tmr" */; SERESSA 2011 – Fernanda Kastensmidt Common used SEE Mitigation Techniques Localized TMR: Only flip-flops are TMR with voters By the user (HDL level description) By the vendor (in the silicon FPGA matrix) Global TMR (also known XTMR) All logic and flip-flops are TMR and voted Clk tree can be also triplicated IOBs can also be triplicated By the user (HDL level description) Reconfiguration SET filtering Usually by the user (HDL level description) Be very aware about synchronization EDAC and other redundancy methods Can be used in by user (HDL description) depending on the FPGA and cases. One time Configurable FPGAs 17 Antifuse FPGA from Actel (Microsemi) RTAX –S/SL 0.15 µm CMOS antifuse process technology, 7 metal layer 1.5V core Embedded memory 350 MHz Antifuse FPGAs SERESSA 2011 – Fernanda Kastensmidt RTAX-S device RAM RAM RAM RAM RAMC SC SC SC SC SC SC RD SC SC SC SC SC SC RAMC SC SC SC SC SC SC RD SC SC SC SC SC SC RAMC SC SC SC SC SC SC RD SC SC SC SC SC SC RAMC RAMC SC SC SC SC SC SC SC SC SC SC SC SC RD SC SC SC SC SC SC SC SC RD SC SC RAMC SC SC SC SC SC SC RD SC SC RAMC SC SC SC SC SC SC RD SC SC RAMC SC SC SC SC SC SC RD SC SC RAMC SC SC SC SC SC SC RD SC SC RX SC SC RAMC RAMC SC SC SC SC SC SC SC SC SC SC SC SC RD RD SC SC SC SC SC SC RAMC SC SC SC SC SC SC RD SC SC RAMC SC SC SC SC SC SC RD SC SC RAMC SC SC SC SC SC SC RD SC SC C C R TXSC SC TXSC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC SC B RXSC SC SC SC SC HD HD HD HD HD HD HD HD HD HD HD HD HD RAMC SC SC SC SC SC SC CT SC SC SC SC SC SC RAMC SC SC SC SC SC SC RD SC SC SC SC SC SC RAMC SC SC SC SC SC SC RD SC SC SC SC SC SC RAMC SC SC SC SC SC SC RD SC SC SC SC SC SC RAMC SC SC SC SC SC SC RD SC SC SC SC SC SC RAMC RAMC SC SC SC SC SC SC SC SC SC SC SC SC RD RD SC SC SC SC SC SC SC SC SC SC SC SC RAMC SC SC SC SC SC SC RD SC SC SC SC SC SC RAMC SC SC SC SC SC SC RD SC SC SC SC SC SC RAMC SC SC SC SC SC SC RD SC SC SC SC SC SC RAMC SC SC SC SC SC SC RD SC SC SC SC SC SC RAMC RAMC SC SC SC SC SC SC SC SC SC SC SC SC RD RD SC SC SC SC SC SC SC SC SC SC SC SC RAMC SC SC SC SC SC SC RD SC SC SC SC SC SC Super Cluster TX TX RX RX [Actel, RTAX-S RadTolerant FPGAs 2007] Antifuse FPGAs C C R RTAX-S device C C-CELL R R-CELL CFN C-CELL D1 D3 B0 B1 FCI D1 D3 B0 B1 CFN Susceptible to SET C Robust to SEU 0 1 0 1 X 0 1 0 1 0 1 0 1 0 1 0 1 X 0 1 X 0 1 FCO Y A1 A0 DB D0 D2 Y A1 A0 DB D0 D2 0 1 ERROR [Actel, RTAX-S RadTolerant FPGAs 2007] Antifuse FPGAs SERESSA 2011 – Fernanda Kastensmidt RTAX-S device Control Logic [Wang et al, NSREC, 03] Logic redundancy design Clock Network Eliminate small leaves in the clock tree User flip-flop Hard-wired triple redundant latch for master and slave Embedded SRAM EDAC macro in FPGA design software (ACTgen) Hamming code detect two error bits, correct one error bit Bit separation: mitigate charge sharing Antifuse FPGAs SERESSA 2011 – Fernanda Kastensmidt RTAX-S: SEU Hardened Techniques [Wang et al, NSREC, 03] C C R Hardened flip-flop (TMR) D1 D3 B0 B1 D1 D3 B0 B1 CFN FCI C-CELL CFN FCI C-CELL 0 1 0 1 comb logic A1 A0 D0 D2 Y A1 A0 DB DB comb logic 0 1 D0 D2 0 1 0 1 0 1 0 1 0 1 0 1 Y 0 1 VHDL / Verilog directly to the FPGA with no modifications as all flip-flops are already hardened by the vendor. Antifuse FPGAs SERESSA 2011 – Fernanda Kastensmidt RTAX-S: SET mitigation by User [Wang et al, NSREC, 03] C C R Hardened flip-flop (TMR) D1 D3 B0 B1 D1 D3 B0 B1 CFN FCI C-CELL CFN FCI C-CELL 0 1 0 1 0 1 0 1 0 1 0 1 SET Filter comb logic A1 A0 DB D0 D2 0 1 Y A1 A0 DB D0 D2 0 1 Y 0 1 0 1 VHDL / Verilog must be modified to add SET filtering. Antifuse FPGAs Antifuse FPGA from Aeroflex UT6325 RadTol Eclipse FPGA 0.25μm, five-layer metal, ViaLinkTM epitaxial CMOS 120 MHz 2.5V core supply voltage Embedded memory Antifuse FPGAs SERESSA 2011 – Fernanda Kastensmidt RadHard Eclipse FPGA ERROR X hardened flip-flops Robust to SEU ViaLink connections Antifuse FPGAs SEU hardened Technique Hardened flip-flop by vendor: based on DICE DICE Memory Cell [Calin, 96] Vdd Vdd Vdd Vdd MP0 MP1 MP2 MP3 A B C D MN0 Vss MN1 Vss MN2 MN3 Vss Vss clk MN4 MN5 MN6 MN7 /D D Embedded memory: EDAC code by user Combination logic: SET filtering by user Antifuse FPGAs One-time configurable FPGA Summary Configuration cells are not sensitive to SEE. Flip-flops are not sensitive to SEU Actel and Aeroflex provides one solution where all flip-flops are hardened. No modifications at HDL is needed for SEU mitigation Logic are susceptible to SETs in high frequency (>100Mhz) The user may protect the logic by using high level mitigation techniques in the HDL description of the design. Redundancy or EDAC is more appropriate than SET filtering, or SET filtering with TMR in flip-flops. Embedded memory EDAC codes implemented by user Antifuse FPGAs SERESSA 2011 – Fernanda Kastensmidt Reconfigurable FPGAs 28 Reconfiguration in space: why? To gain flexibility Reconfiguration has been there for years: Resource optimization due to time sharing Extend the lifetime by adding new functions Bug fixing Updates Download of new software Enabling/disabling of spare modules Reconfigurable FPGAs can bring new possibilities! SERESSA 2011 – Fernanda Kastensmidt FPGA structure/technology SERESSA 2011 – Fernanda Kastensmidt What about space? Reconfigurable FPGAs: Configuration memory must be changeable on-the-fly Multiple configuration images must be stored Space environment can alter configuration information Challenges: Understand the problem Identify suitable error mitigation techniques SERESSA 2011 – Fernanda Kastensmidt SRAM-based FPGA Architecture Xilinx Virtex-4QV BRAM Lookup Table CLB (LUT) A B C D 0 1 PowerPC 1 1 1 1 1 1 0 Boolean Function F(A,B,C,D) ‘0’ 1 PowerPC 0 0 1 DSP 0 1 0 SRAM-based FPGAs 32 SEU in SRAM-based FPGAs: CLB slice I1 I2 I3 I4 LUT CLB slice 0 0 0 1 0 1 1 1 0 0 0 1 0 1 1 1 Transient Effect (corrected at next ffp load) LUT routing Persistent effect (corrected by scrubbing) SRAM-based FPGAs Configuration memory bits SERESSA 2011 – Fernanda Kastensmidt 33 SET in SRAM-based FPGAs : CLB slice I1 I2 I3 I4 LUT CLB slice 0 0 0 1 0 1 1 1 0 0 0 1 0 1 1 1 X SET may be captured by the ffp. LUT routing Transient Effect (corrected at next ffp load) SRAM-based FPGAs Configuration memory bits 34 SRAM-based FPGA General Routing Matrix (GRM) Xilinx Virtex-4QV Direct lines Long lines CLB CLB CLB Hex connections CLB CLB CLB CLB CLB CLB CLB Fast connect Double lines CLB SRAM-based FPGAs CLB CLB CLB Hex lines CLB CLB Direct connections CLB CLB CLB CLB 35 CLB SEU in SRAM-based FPGAs: Routing configuration cells Xilinx Virtex-4QV Direct connections: 0 Hex connections: 1 open open short short 1 short 0 0 1 1 1 open Persistent effect (corrected by scrubbing) SRAM-based FPGAs SERESSA 2011 – Fernanda Kastensmidt 36 Other sensitive structures Power-on Reset (POR) • Low probability of occurrence • Signature: done pin transitions low, I/O becomes tristated, no user functionality available • Solution: reconfigure device SelectMAP and JTAG controllers • Low probability of occurrence • Signature: loss of communication, read access to configuration memory returns constant value. • Solution: reconfigure device Single-Event-Functional Interrupts (SEFI) Digital Clock Manager (DCM) Input and Output Blocks (IOB) Power-PC Hard IP Multi-Gigabit Transceivers (MGT) SRAM-based FPGAs 37 Flash-based FPGA ProAsic3 /RT3P Flash-based FPGAs SEE sensitivity Configurable Logic Block called VersaTile VersaTile logic Flash-based FPGAs Effect 1: SET in the logic SERESSA 2011 – Fernanda Kastensmidt SEE sensitivity Configurable Logic Block called VersaTile VersaTile X ffp Flash-based FPGAs Effect 2: SEU in the ffp SERESSA 2011 – Fernanda Kastensmidt SEE sensitivity Floating Gate (FG) switch Effect 3: SET in the logic path SET in the routing path Flash-based FPGAs SERESSA 2011 – Fernanda Kastensmidt SEE Mitigation Techniques Design-level solutions: Use non rad-hard FPGAs (military / COTS): Design-level and architectural-level mitigation Place and route mitigation Device-level solutions: Use rad-hard FPGAs by construction (Virtex-5QV , ATF280), based on 12T memory elements, plus glitch filtering and ECC Flash-based FPGAs SERESSA 2011 – Fernanda Kastensmidt SEE Mitigation Techniques Different types of mitigations according to the FPGA sensitivity Implemented by user: SEE mitigation techniques at design and architecture level: VHDL or Verilog; and at EDA level: place&route Soft FPGAs (COTS/Military) SRAM-based FPGAs: Virtex families [Xilinx] - Virtex-4QV (Space-grade) FLASH-based FPGAs: ProASIC families [Actel] design FPGA Flash-based FPGAs SRAM-based FPGAs SERESSA 2011 – Fernanda Kastensmidt Design Flow Mitigation for SRAM-based FPGAs HDL design TMR by hand ISE tool Placement Routing ISE tool Synthesis optimizations configuration bitstream … 101001110100000111… Scrubbing (full or partial reconfiguration) SRAM-based FPGAs Logic mapping Placement Routing 10101011.. output Fault Injection (fault tolerance verification) SERESSA 2011 – Fernanda Kastensmidt SEE mitigation for SRAM-based FPGAs Scrubbing: full or partial reconfiguration XQR18V04 BOOT DATA[7:0] OE/RESET CE GND CLK EEPROM Original bitstream XQR18V04 SCRUB DATA[7:0] OE/RESET CE GND CLK OSC SRAM-based FPGAs 10101000101 FPGA DATA[7:0] INIT Configuration bits DONE 00000001010 00000001010 CS 10101010100 10101010100 WR I/O I/O SCRUB Controller I/O I/O 10101010010 10101010010 10101010101 10101000101 01010100101 01010100101 11111111101 11111111101 11100000000 11100000000 11101010101 11101010101 10101010101 10101010101 00101000010 00101000010 CCLK SERESSA 2011 – Fernanda Kastensmidt Scrubbing Method Scrubbing can be performed: from outside the FPGA by another FPGA controller from inside the FPGA: Hardware Internal Configuration Access Port (HWICAP) SRAM-based FPGAs SERESSA 2011 – Fernanda Kastensmidt SEE mitigation for SRAM-based FPGAs Global TMR (also known XTMR) All logic and flip-flops are TMR and voted clk tree triplicated IOBs triplicated Implemented by the user (HDL level description) or by tool FPGA REDUNDANT LOGIC (tr2) REDUNDANT LOGIC (tr1) REDUNDANT LOGIC (tr2) REDUNDANT LOGIC (tr0) REDUNDANT LOGIC (tr1) REDUNDANT LOGIC (tr2) TMR Output Voter REDUNDANT LOGIC (tr1) REDUNDANT LOGIC (tr0) TMR flip-flop INPUT TMR flip-flop REDUNDANT LOGIC (tr0) package PIN package PIN granularity SRAM-based FPGAs OUTPUT SERESSA 2011 – Fernanda Kastensmidt FPGA REDUNDANT LOGIC (tr2) REDUNDANT LOGIC (tr1) REDUNDANT LOGIC (tr2) TMR Output Voter REDUNDANT LOGIC (tr1) TMR flip-flop INPUT REDUNDANT LOGIC (tr0) TMR flip-flop REDUNDANT LOGIC (tr0) REDUNDANT LOGIC (tr0) REDUNDANT LOGIC (tr1) REDUNDANT LOGIC (tr2) OUTPUT package PIN package PIN TMR flip-flop OK tr0 tr1 tr2 clk0 clk1 clk2 X OK OK MAJ MAJ MAJ The recovery path is mandatory to correct the state of the flipflops, specially in FSM. R0 R1 R2 OK OK 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 MAJ 0 0 0 1 0 1 1 1 LUT: 00010111_00010111 SRAM-based FPGAs SERESSA 2011 – Fernanda Kastensmidt 48 FPGA REDUNDANT LOGIC (tr2) REDUNDANT LOGIC (tr1) REDUNDANT LOGIC (tr2) REDUNDANT LOGIC (tr0) REDUNDANT LOGIC (tr1) REDUNDANT LOGIC (tr2) TMR Output Voter REDUNDANT LOGIC (tr1) REDUNDANT LOGIC (tr0) TMR flip-flop INPUT TMR flip-flop REDUNDANT LOGIC (tr0) OUTPUT package PIN package PIN REF R0 R1 R2 MAJ 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 0 0 1 1 0 0 0 0: it allows the data to pass to the output pad. 1: it blocks the data LUT: 00011000_00011000 SRAM-based FPGAs R0 X O_voter 3-state_0 1 R0 X R1 OK O_voter 3-state_1 0 R1 OK R2OK O_voter 3-state_2 R2 SERESSA 2011 – Fernanda Kastensmidt 0 OK 49 Embedded Memory (BRAM): EDAC Virtex5: XQR5VFX130’s from Xilinx BRAM blocks are configurable as 512 64-bit RAM with 8-bit error correcting code (ECC) bits for every 64-bit word. The 8-bit ECC parity checksum detect and correct single-bit errors, and detect (but not correct) double-bit errors. For every word read, the 72-bits are fed into an ECC decoder which generates status bits indicating: no error, single-bit error detected and corrected, or double-bit error detected. [Allen et al., TNS 2010] SRAM-based FPGAs SERESSA 2011 – Fernanda Kastensmidt Embedded memory (BRAM): TMR Upsets in BRAMs are not corrected by scrubbing. TMR with refreshing can be used to mitigate upsets. Need to use Dual Port BRAMs. OK X Mechanism to refresh the memory contents Counter Voters SRAM-based FPGAs SERESSA 2011 – Fernanda Kastensmidt OK SEE in Embedded Processor PowerPC Software-based techniques Duplication of variables with comparisons (data fault effects) Basic block signatures (control flow fault effects) Watch-dog and self-checking blocks (improve control flow fault effects) Two Power-PCs for detection and recomputation [Bernardi, et al,, TNS, 2006] [Azambuja, et al, TNS, 2011] SRAM-based FPGAs SERESSA 2011 – Fernanda Kastensmidt Problem: Domain Crossing Events Bit-flips in the routing can generate short cut connections among different blocks of the TMR (tr0, tr1 and tr2). upset INPUT REDUNDANT OK LOGIC (tr1) REDUNDANTOK LOGIC (tr2) package PIN OK tr0 OK tr1 OK tr2 TMR Output Majority Voter REDUNDANTX LOGIC (tr0) TMR register with voters and refresh FPGA OUTPUT package PIN Upset affects only the redundant logic tr0, consequently, the majority voter choose the correct result (two out of three outputs). SRAM-based FPGAs SERESSA 2011 – Fernanda Kastensmidt Problem: Domain Crossing Events Bit-flips in the routing can generate short cut connections among different blocks of the TMR (tr0, tr1 and tr2). upset INPUT REDUNDANT OK LOGIC (tr1) REDUNDANT LOGIC (tr2) package PIN X X tr0 X tr1 X tr2 TMR Output Majority Voter REDUNDANT X LOGIC (tr0) TMR register with voters and refresh FPGA OUTPUT package PIN Upset affects two redundant logic modules, consequently, the majority voter may choose the wrong result (two out of three outputs). SRAM-based FPGAs SERESSA 2011 – Fernanda Kastensmidt Problem: Domain Crossing Events Bit-flips in the routing can generate short cut connections among different blocks of the TMR (tr0, tr1 and tr2). Signal: tr0_comp/N$302 Redundant 0 upset Signal: counter6/counter/I$26/tr2_count(1) Redundant 2 SRAM-based FPGAs SERESSA 2011 – Fernanda Kastensmidt Problem: Domain Crossing Events According to the location of the upsets, more than one CLB or routing connections can be affected generating error in more than one TMR redundant part. ~5% of the upsets in the routing may result on this type of fault Multiple bit upsets due to: High density and small dimensions of the configuration memory cells. Charge sharing SRAM-based FPGAs SERESSA 2011 – Fernanda Kastensmidt Solution for Domain Crossing Events Use dedicated placement and routing to minimize domain cross-section and vulnerable bit upsets. RoRa: Reliability-Oriented Place and Route Algorithm RORA [Sterpone, L. Electronics System Design Techniques for Safety Critical Applications Publisher Springer, 2008] SRAM-based FPGAs SEE Mitigation in Flash-based FPGAs Considering only SEU effect: Local TMR EDAC (hamming code) ProAsic3 /RT3P Considering SET and SEU effects: Global TMR SET filtering System redundancy and checkers Etc… User can protect the design at HDL level as in a ASIC! Flash-based FPGAs SERESSA 2011 – Fernanda Kastensmidt SEU mitigation for FLASH-based FPGAs Local TMR: Only flip-flops are TMR with voters Implemented: By the user (HDL level description) By the vendor (in the silicon FPGA matrix) ProAsic3 /RT3P FPGA LOGIC TMR Output Voter LOGIC TMR flip-flop Flash-based FPGAs LOGIC TMR flip-flop INPUT SERESSA 2011 – Fernanda Kastensmidt OUTPUT FPGA package PIN TMR Output Voter REDUNDANT LOGIC (tr0) TMR flip-flop REDUNDANT LOGIC (tr0) TMR flip-flop INPUT REDUNDANT LOGIC (tr0) OUTPUT package PIN TMR flip-flop clk X OK clk clk Flash-based FPGAs OK OK MAJ R0 R1 R2 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 MAJ 0 0 0 1 0 1 1 1 SERESSA 2011 – Fernanda Kastensmidt 60 SEU&SET mitigation for FLASH-based FPGAs TMR & SET filtering Implemented usually by the user (HDL level description) Be very aware about performance degradation Added delay is proportional to the SET pulse width intended to be filtered. FPGA Delay x1 Delay x2 Flash-based FPGAs LOGIC Delay x1 Delay x2 TMR Output Voter LOGIC TMR flip-flop INPUT SERESSA 2011 – Fernanda Kastensmidt OUTPUT FPGA Delay x2 Delay x1 Delay x2 TMR Output Voter Delay x1 LOGIC TMR flip-flop LOGIC INPUT OUTPUT clk logic0 OK clk Delay x1 clk X MAJ logic1 logic2 OK ffp0 ffp1 ffp2 Delay x2 clk OK MAJ Frequency penalty is proportional to Delay Flash-based FPGAs 62 SEU & SET mitigation in Flash-based FPGA VersaTile VersaTile VersaTile VersaTile ffp logic logic MAJ VersaTile VersaTile ffp delay VersaTile VersaTile delay delay VersaTile ffp VHDL / Verilog must be modified to add SET filtering and TMR Flash-based FPGAs SERESSA 2011 – Fernanda Kastensmidt SEE Mitigation Techniques Different types of mitigations according to the FPGA sensitivity RadHard SRAM-based FPGAs Virtex-5QV (Space-grade) - SIRF [XILINX] ATF280E [ATMEL] design Implemented by vendor: Device level and Hardening by Design (RHBD) techniques at the FPGA FPGA matrix logic gates and flip-flops Flash-based FPGAs SERESSA 2011 – Fernanda Kastensmidt ATF280 Reprogrammable RadTol FPGAs From Atmel SRAM-based FPGAs SERESSA 2011 – Fernanda Kastensmidt Mitigation Techniques in ATF280 Layout rules to mitigate charge sharing SEU hardened Memory cells (12T) Core cell Flip-Flops, embedded memory, configuration memory based on radiation hardened Flip-Flops Controller protected by classical TMR RAM address decoders, clock and reset trees Protected by DMR (resistive isolation path based on N and P isolated path carrying the same signal) Isolation path to filter SET [BANCELIN, MAPLD 2009] SRAM-based FPGAs SERESSA 2011 – Fernanda Kastensmidt Device-level SEE Mitigation in ATF280E FPGA SEU Hardened Flip-flop Isolation path for SET [BANCELIN, MAPLD 2009] SRAM-based FPGAs SERESSA 2011 – Fernanda Kastensmidt Xilinx SIRF FPGA Virtex-5QV (Space-grade) 65nm CMOS process SEU hardened flip-flops: All configuration SRAM cells All user flip-flops (CLB) SET filtering structure that can be configured on or off when configuring the FPGA. BRAMs have EDAC with refreshing to avoid accumulation of errors. SRAM-based FPGAs SERESSA 2011 – Fernanda Kastensmidt Resource Comparison ANTIFUSE SEU Equiv. Gates (4-LUT) FLASH SRAM 1.5 K 40 K 75 K 180 K 14 K 3K 20 K 75 K 180 K 14 K Dist. Mem (bits) - - - 1,000 K - Emb. Mem (bits) 55 K 504 K 504 K 6,000 K 115 K - 120 - 96 - 0.25μm 0.15μm FFps DSP modules [From Vendor Datasheets] or 0.13μm 0.09μm SERESSA 2011 – Fernanda Kastensmidt 0.18μm SEE Mitigation techniques ANTIFUSE SET SEU Config. bits SET filtering or global TMR None None FLASH SET filtering with localized TMR / EDAC / global TMR / others None None SRAM None* Global TMR None Scrubbing SERESSA 2011 – Fernanda Kastensmidt None SEE Summary ANTIFUSE SEU FLASH SRAM Satured crossSection (cm2/ffp) Embedded memory 2E-7 4E-9 4E-8 3E-8 Flip-flop 5E-7 1E-9 2E-7 7E-7 Embedded memory 64 30 1 0.2 Flip-flop 42 37 6 0.5 0.25μm 0.15μm LETth MeV-cm2/mg 0.13μm *With mitigation: SEE immunity < 43 MeV-cm2/mg 0.09μm SEE Summary ANTIFUSE SEU FLASH SRAM Error Rate per bit Embedded memory 4.8E-11 4.4E-12 4E-8 7E-7 2.8E-10 7.0E-13 5E-9 2E-6 Flip-flop 0.25μm 0.15μm 0.13μm The final Error Rate depends on your final design! 0.09μm TID and SEL effects in FPGAs ANTIFUSE TID SEL free 300 krad (si) < 120 Mev-cm2/mg 300 krad (si) < 117 Mev-cm2/mg FLASH < 40 krad (si) < 96 Mev-cm2/mg SRAM 300 krad (si) < 125 < 70 Mev-cm2/mg Mev-cm2/mg SERESSA 2011 – Fernanda Kastensmidt TID Effects in ProASIC3 / RT3P Logic is fabricated in 130nm and it presents electrical degradations that follows ASIC degradation. Floating gate (FG) transistor show degradation in: Vth shifts Leakage current Lost of charge Degradation in Charge-pump and control circuits. 27/09/2010 ESTEC TID Test: Co-60 source ProAsic3 FPGA Rate: 1.749 krad(Si)/h 0.48 rad(Si)/s At IEAv in São Jose dos Campos, Brazil Current & Temperature x krads(Si) 0.060000 Power supply DC current (A) 0.055000 0.050000 0.045000 0.040000 0.035000 0.030000 0.025000 0.020000 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 Accumulated dose (krad(Si)) 29.00 28.80 28.60 Temperature (Celsius) 28.40 28.20 28.00 27.80 27.60 27.40 27.20 27.00 26.80 0 5 10 15 20 25 30 35 40 45 50 55 Accumulated dose (krad(Si)) 60 65 70 75 80 TID effect Propagation Delay Degradation in ProASIC3 (130nm technology) [Kastensmidt et al, TNS, 2011] SERESSA 2011 – Fernanda Kastensmidt 1000 Avg1 (caseA & caseB) - measured Avg2 (caseC) - measured % Propagation-delay Degradation Avg3 (caseD) - measured Avg (all) - measured 100 10 1 0 3 6 10 13 17 20 24 27 31 34 38 41 45 48 52 Acummulated dose (krad(Si)) 27/09/2010 ESTEC 55 59 62 69 Conclusions Reconfigurable computing could be a breakthrough for certain space applications However, space is a very conservative business and may deem reconfigurable computing as too risky Sensitivity of devices to radiations Complexity of the design and validation process Enabling technology still not mature enough: Virtex 5 QV is ITAR and unknown AT280 is too small and low performing RT3P is not yet as capable as high-end SRAM FPGAs SERESSA 2011 – Fernanda Kastensmidt Thank You! Fernanda Lima Kastensmidt Universidade Federal do Rio Grande do Sul (UFRGS) Contact: [email protected]
