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DSF Nios II
Digitale Signalverarbeitung mit FPGA Digitale Signalverarbeitung mit FPGA (DSF) Soft Core Prozessor NIOS II Stand Mai 2007 Jens Onno Krah Cologne University of Applied Sciences www.fh-koeln.de NIOS II [email protected] 1 Digitale Signalverarbeitung mit FPGA 1 What is Nios II? Altera’s Second Generation Soft-Core 32 Bit RISC Microprocessor Debug On-Chip ROM On-Chip RAM FPGA NIOS II 2 Digitale Signalverarbeitung mit FPGA Krah SS 2007 NIOS II Avalon Switch Fabric Nios II CPU Cache −- Nios Developed By Altera II Plus Internally All Peripherals Written In HDL −- Can Harvard Architecture Be Targeted For All Altera FPGAs −- Synthesis Royalty-Free Using Quartus II Integrated Synthesis UART GPIO Timer SPI SDRAM Controller Digitale Signalverarbeitung mit FPGA Problem: Reduce Cost, Complexity & Power Flash I/O CPU SDRAM I/O I/O I/O I/O I/O DSP FPGA CPU DSP Solution:: Replace External Devices Solution with Programmable Logic NIOS II 3 Digitale Signalverarbeitung mit FPGA FPGA Hardware Design Flow Design Entry/RTL Coding Design Specification SOPC Builder - Behavioral or Structural Description of Design RTL Simulation Functional Simulation (Modelsim, - Functional Simulation (Modelsim, Quartus II) Quartus II) Verify Logic Model & Data Flow - Verify Logic Model & Data Flow (No Timing Delays) (No Timing Delays) LE M512 M4K I/O Synthesis - Translate Design into Device Specific Primitives - Optimization to Meet Required Area & Performance Constraints - Spectrum, Synplify, Quartus II Place & Route - Map Primitives to Specific Locations Inside Target Technology with Reference to Area & Performance Constraints - Specify Routing Resources to Be Used NIOS II 4 Digitale Signalverarbeitung mit FPGA Krah SS 2007 NIOS II Digitale Signalverarbeitung mit FPGA FPGA Hardware Design Flow Timing Analysis tclk - Verify Performance Specifications Were Met - Static Timing Analysis Gate Level Simulation - Timing Simulation - Verify Design Will Work in Target Technology Test FPGA on PC Board - Program & Test Device on Board - Use SignalTap II for Debugging NIOS II 5 Digitale Signalverarbeitung mit FPGA DBC2C20 NIOS II Development Kit USB OTG 2x CAN Phy 4x RS485 Phy Download /JTAG Debug Connector RS232 Phy 24pin 3V3 GPIO Temperature Sensor 16 MB SDRAM 8 MB Flash Power Connector 24V I/O Buttons 7-Segment Anzeige Power LED LEDs LVDS I/O NIOS II 6 Digitale Signalverarbeitung mit FPGA Krah SS 2007 NIOS II 10/100 Ethernet PHY & RJ-45 Connector Digitale Signalverarbeitung mit FPGA Reference Designs For Dev Kits Several reference designs are available See altera\kits\nios2.60\examples\verilog or altera\kits\nios2.60\examples\vhdl NIOS II 7 Digitale Signalverarbeitung mit FPGA Standard Design Block Diagram 8MB FLASH 16MB SDRAM RS232 Driver RS485 Driver SDRAM Controller UART UART Nios II Processor Address (32) Write Data Out (32) IRQ IRQ On-Chip NIOS II Off-Chip 8 Digitale Signalverarbeitung mit FPGA Krah SS 2007 NIOS II Tri-State Bridge ROM (with Monitor) General Purpose Timer Periodic Timer LED PIO Button PIO GPIO 3 LEDs Buttons Header Ethernet 10/100 MAC CAN CAN Driver Ethernet Phy Data In (32) Avalon Switch Fabric 32-Bit Nios II Processor Read Digitale Signalverarbeitung mit FPGA Nios II System Architecture Instr. Nios II CPU Address Decoder Data Interrupt Controller On-Chip Debug Core UART 0 Avalon Master/ Slave Port Interfaces Timer 0 SPI 0 Wait State Generation GPIO 0 Data in Multiplexer Off-Chip Software Trace Memory DMA 0 Master Arbitration Dynamic Bus Sizing Avalon Switch Fabric NIOS II UART n Timer n SPI n GPIO n DMA n Memory Interface Memory Interface User-Defined InterfaceUser-Defined Interface 9 Digitale Signalverarbeitung mit FPGA Nios II Processor Architecture Classic Pipelined RISC Machine − 32 General Purpose Registers − 3 Instruction Formats − 32-Bit Instructions − 32-Bit Data Path − Separate Instruction and Data Cache (configurable sizes) − Branch Prediction − 32 Prioritized Interrupts − Custom Instructions − JTAG-Based Hardware Debug Unit NIOS II 10 Digitale Signalverarbeitung mit FPGA Krah SS 2007 NIOS II Digitale Signalverarbeitung mit FPGA Nios II Block Diagram Nios II Processor Core reset clock JTAG interface to Software Debugger HardwareAssisted Debug Module Program Controller & Address Generation General Purpose Registers r0 to r31 Instruction Master Port Instruction Cache Exception Controller Interrupt Controller irq[31..0] Custom I/O Signals NIOS II Custom Instruction Logic Control Registers ctl0 to ctl4 Arithmetic Logic Unit Data Cache Data Master Port 11 Digitale Signalverarbeitung mit FPGA Nios II Versions Nios II Processor Comes In Three ISA Compatible Versions − FAST: Optimized for Speed − STANDARD: Balanced for Speed and Size − ECONOMY: Optimized for Size Software − Code is Binary Compatible NIOS II No Changes Required When CPU is Changed 12 Digitale Signalverarbeitung mit FPGA Krah SS 2007 NIOS II Digitale Signalverarbeitung mit FPGA Binary Compatibility / Flexible Performance Nios II /f Fast Nios II /s Standard Nios II /e Economy Pipeline 6 Stage 5 Stage None H/W Multiplier & Barrel Shifter 1 Cycle 3 Cycle Emulated In Software Branch Prediction Dynamic Static None Instruction Cache Configurable Configurable None Data Cache Configurable None None 1400 - 1800 1200 – 1400 600 – 700 Logic Usage (Logic Elements) Custom Instructions NIOS II Up to 256 13 Digitale Signalverarbeitung mit FPGA Hardware Multiplier Acceleration Nios II Economy version - No Multiply Hardware − Uses GNUPro Math Library to Implement Multiplier Nios II Standard - Full Hardware Multiplier − 32 x 32 32 in 3 Clock Cycles if DSP block present, else uses software only multiplier Nios II Fast - Full Hardware Multiplier − 32 x 32 32 in 1 Clock Cycles if DSP block present, else uses software only multiplier Acceleration Clock Cycles Hardware (32 x 32 32) None NIOS II 14 Digitale Signalverarbeitung mit FPGA Krah SS 2007 NIOS II 250 Standard MUL in Stratix 3 Fast MUL in Stratix 1 Digitale Signalverarbeitung mit FPGA Hardware Multiplier Support Stratix and Stratix II DSP Blocks Cyclone II Multiplier Blocks − Multiplication using 18 x 18 Multiplier Block Optional LE Implementation − Enables HW multiplier support for Cyclone Device Family − Can also use in Stratix and Stratix II instead of DSP Blocks − Mul, Shift, Rotate (~ 8 Clocks Per Mul) − Eliminates need for DSP blocks for Nios II MUL NIOS II 15 Digitale Signalverarbeitung mit FPGA Variation with FPGA Device 250 Fast DMIPS 200 150 Standard 100 50 Economy 0 0 500 1000 1500 Logic Elements Stratix II NIOS II 16 Digitale Signalverarbeitung mit FPGA Krah SS 2007 NIOS II Stratix Cyclone HC-Stratix 2000 Digitale Signalverarbeitung mit FPGA SOPC Builder - System Contents IRQ Priorities Connection Panel Address Map Clock Domains Component NIOS II 17 Digitale Signalverarbeitung mit FPGA Insert Peripherals Including Nios II Processor Double-click on peripheral or press Add… Build up memory map of your embedded system Eg. System Memory Space 0x001000000 SDRAM 0x000800000 Other Peripherals 0x000400000 Flash 0x0 NIOS II 18 Digitale Signalverarbeitung mit FPGA Krah SS 2007 NIOS II Digitale Signalverarbeitung mit FPGA Quartus II Project Directories Hardware − HDL Source & Netlist − db - Quartus project database Software − Application source code − Library files All other Quartus II and SOPC Builder System files … Simulation − ModelSim project − Automatically generated test memory and vectors NIOS II 19 Digitale Signalverarbeitung mit FPGA SOPC Builder Flow SOPC Builder GUI Processor Library Configure Processor Custom Instructions Peripheral Library Select & Configure Peripherals, IP IP Modules Hardware Development Software Development Nios II IDE Connect Blocks HDL Source Files Testbench Generate Hardware Configuration File Synthesis & Fitter Verification & Debug JTAG, Serial, or Ethernet User Design Other IP Blocks Altera PLD Quartus II NIOS II 20 Digitale Signalverarbeitung mit FPGA Krah SS 2007 NIOS II Executable Code On-Chip Debug Software Trace Hard Breakpoints SignalTap® II C Header files Custom Library Peripheral Drivers Compiler, Linker, Debugger User Code Libraries RTOS GNU Tools Digitale Signalverarbeitung mit FPGA Running Code On A Target Nios II IDE can be used to download code to target board NIOS II 21 Digitale Signalverarbeitung mit FPGA Running Code On A Target Download messages, stdout and stdin appear in console window NIOS II 22 Digitale Signalverarbeitung mit FPGA Krah SS 2007 NIOS II Digitale Signalverarbeitung mit FPGA System ID Peripheral Revisited When downloading code to a target, Nios II IDE computes expected System ID peripheral values from PTF file − If computed ID values do not match System ID variables stored on the target board then an error is flagged − Generally, to fix this you should recompile your hardware NIOS II To disable this option see Run > Run Main Page 23 Digitale Signalverarbeitung mit FPGA Avalon Switch Fabric Proprietary interconnect specification used with Nios II Principal design goals Nios II Processor 32-Bit Nios II Processor Transfer Types − − − − − NIOS II Slave Transfers Master Transfers Streaming Transfers Latency-Aware Transfers Burst Transfers 24 Digitale Signalverarbeitung mit FPGA Krah SS 2007 NIOS II Switch PIO Address (32) Read Write Data In (32) Data Out (32) IRQ IRQ #(6) ROM (with Monitor) UART Timer Avalon Switch Fabric − Low resource utilization for bus logic − Simplicity − Synchronous operation LED PIO 7-Segment LED PIO PIO-32 UserDefined Interface Digitale Signalverarbeitung mit FPGA Nios II - Leads The Industry Highest Performance Multi-Processor Hardware Acceleration Custom Instructions Greatest Flexibility Processors Peripherals Optimized Interconnect Most Powerful Design Tools Fastest Time to Market NIOS II 25 Digitale Signalverarbeitung mit FPGA Krah SS 2007 NIOS II SOPC Builder Nios II IDE On-Chip Processor Debug SignalTap® II Logic Analyzer Concept to System in Minutes FPGA > HardCopy Structured ASIC
